Significant advances in silicon densities have allowed for the integration of many functions onto a single silicon chip. With this increased density, many of the peripherals in a computer system that were normally attached to the processor via an external bus now are attached via a on-chip bus. In addition, the bandwidth requirements of these on-chip buses are increasing due to the integration of various audio, video, and graphic functions along with the processor. As a result, achieving maximum on-chip bus performance is a concern.
FIG. 1 illustrates a conventional on-chip bus architecture 100 containing a on-chip bus 120 and bus arbiter 140. The on-chip bus 120 supports read and write data transfers between master devices 110 and slave devices 130 equipped with a on-chip bus interface. A "master" device is one which requests access to or control of the on-chip bus 120 and transmits and receives data across the on-chip bus 120. A "slave" device is one which transmits or receives data across the on-chip bus 120 and is responsive to a master. The slave may not request access to or control of the on-chip bus 120. Access to the on-chip bus 120 is granted through an arbitration mechanism 140, or arbiter, which is attached to the on-chip bus 120 and prioritizes all transfer requests from master device for bus ownership. Timing for all on-chip bus signals is provided by a single clock source (not shown). This single clock source is shared by all master devices and slave devices attached to the on-chip bus 120. The master devices may operate at a different (higher) frequency. Synchronization logic may be implemented at the interface of the two clock domains.
One approach to increasing the performance of the on-chip bus is to use multiple parallel high speed buses instead of a single bus as illustrated in FIG. 1. A mechanism, such as a conventional cross-bar switch, is typically utilized to allow these buses to communicate with each other. However, conventional mechanisms do not prioritize requests from different master buses. The conventional cross-bar switches do not provide for arbitration between the buses. Since each bus contains its own arbiter for arbitrating only the master device attached to that bus, this would significantly limit the efficiency of the system.
Accordingly, there exists a need for a method and system for prioritizing requests between multiple parallel high speed buses. This method should minimize the latency between data transfers to and from master devices with the highest priority. The present invention addresses such a need.